Evolvable Hardware
Nature is phenomenal. The achievements in, for example, evolution are everywhere to be seen: complexity, resilience, inventive solutions and beauty. Evolvable Hardware (EH) is a field of evolutionary computation (EC) that focuses on the embodiment of evolution in a physical media. If EH could achieve even a small step in natural evolution’s achievements, it would be a significant step for hardware designers. Before the field of EH began, EC had already shown artificial evolution to be a highly competitive problem solver. EH thus started off as a new and exciting field with much promise. It seemed only a matter of time before researchers would find ways to convert such techniques into hardware problem solvers and further refine the techniques to achieve systems that were competitive with or better than human designs.
76 Evolvable hardware is a concept that integrates reconfigurable hardware, artificial intelligence, fault tolerance, and autonomous systems to design computer hardware systems, especially those that must keep working when no maintenance is possible. Evolvable hardware (EHW) utilises genetic algorithms to create circuit solutions given only limited information, such as the circuits desired functionality. Evolution then determines the circuits structure given the building blocks presented to it (these normally include primitive blocks such as AND gates for digital circuit design).
However, 15 years on—it appears that problems solved by EH are only of the size and complexity of that achievable in EC 15 years ago and seldom compete with traditional designs. A critical review of the field is presented. Whilst highlighting some of the successes, it also considers why the field is far from reaching these goals. The paper further redefines the field and speculates where the field should go in the next 10 years. Yao and Higuchi published a paper in 1999 entitled “Promises and Challenges of Evolvable Hardware” which reviewed the progress and possible future direction of what was then a new field of research, Evolvable Hardware.
A little more than 10 years on, this paper considers the progress of this research field, both in terms of the successes achieved to date and also the failure to fulfil the promises of the field highlighted in the 1999 paper. Through a critical review of the field, the authors’ intention is to provide a realistic status of the field today and highlight the fact that the challenges remain, redefine the field (what should be considered as Evolvable Hardware) and propose a revised future path.In the mid 1990s, researchers began applying Evolutionary Algorithms (EAs) to a computer chip that could dynamically alter the hardware functionality and physical connections of its circuits –.
This combination of EAs with programmable electronics, e.g. Field Programmable Gate Arrays (FPGAs) & Field Programmable Analogue Arrays (FPAAs), spawned a new field of EC called Evolvable Hardware.The EH field has since expanded beyond the use of EAs on simple electronic devices to encompass many different combinations of EAs and biologically inspired algorithms (BIAs) with various physical devices or simulations thereof.
Further, the challenges inherent in EH have led researchers to explore new BIAs that may be more suitable as techniques for EH.In this paper we will define the field of EH and split the field into the two related, but different sub-fields: Evolvable Hardware Design (EHD) and Adaptive Hardware (AH).Evolvable Hardware, as the name suggests, should have a connection to embodiment in a real device. However, in a number of EH papers, results produced are interpreted as hardware components e.g. Logic gates, illustrated as a circuit diagram and justified as a hardware implementation despite the lack of a realistic hardware simulator.
In this paper such work is not considered as Evolvable Hardware. The lack of grounding in real hardware, either physical or through realistic simulators, defies their inclusion in the field of EH. In other cases, authors attempt to speed up their EC process by implementing part or all of the BIA in hardware.
In other words, hardware accelerators and certainly not, as defined in this paper, Evolvable Hardware.In this paper we define the field of Evolvable Hardware (EH) as the design or application of EAs and BIAs for the specific purpose of creating physical devices and novel or optimised physical designs.With this in mind, there are some successes in the field including analogue and digital electronics, antennas, MEMS chips, optical systems as well as quantum circuits. Section presents an overview of some of these successes.However, let’s step back for a minute and consider what evolving hardware should consist of. Figure illustrates an example of EH where an accurate model of the device physics is applied to produce the fitness function used to evaluate the efficacy of the circuits. So while the evolutionary loop is using no hardware, the simulation models used are very accurate with respect to the final physical system (in this case transistors with variable characteristics). Other forms of realistic hardware designs may include device simulators, as in , or actual physical devices, as in. Such work can be classed under the subfield of Evolvable Hardware Design.
The goal is novel or optimised non-adaptive hardware designs, either on physical hardware or as solutions generated from realistic simulators.The sub-field of Adaptive Hardware can be defined as the application of BIAs to endow real hardware, or simulations thereof, with some adaptive characteristics. These adaptive characteristics enable changes within the EH design/device, as required, so as to enable them to continue operating correctly in a changing environment.
Such environmental pressure may consist of changes in the operational requirements i.e. Functionality change requirements, or maintenance of functionality e.g. Robustness, in the presence of faults.
Examples of such Adaptive Hardware include an FPAA that can change its function as operational requirements change or a circuit on an FPGA that can “evolve” to heal from radiation damage.The remainder of the paper is structured as follows: Sect. Provides a definition of the field together with the inherent advantages one can expect from such a field. Some actual success stories are reviewed in a little more detail in Sect. Section considers many of the challenges that still face the community.
Some newer approaches that are, or might be, applied to evolvable hardware are discussed in Sect. Section provides some thoughts on the future of evolvable hardware and Sect. Concludes with a short summary. Evolvable hardware characteristicsIn the literature, it is difficult to find a set of characteristics that the community has agreed upon for what characterises an EH system.
Indeed most work does not address this issue at all. Possible advantages of evolvable hardwareEvolvable Hardware is a method for circuit or device design (within some media) that uses inspiration from biology to create techniques that enable hardware designs to emerge rather than be designed. At first sight this would seem very appealing. Consider two different systems, one from nature and one human engineered: the human immune system (nature design) and the computer that we are writing this paper on (human design). Which is more complex? Which is most reliable? Which is optimised most?
Which is most adaptable to change?The answer to almost all such questions is the human immune system. This is usually the case when one considers most natural systems. Possibly the only winner from the engineered side might be the question, “Which is optimised most?”.
However, this will depend on how you define optimised. While this is appealing, anyone that has used any type of evolutionary system knows that it is not quite that straightforward. Nature has a number of advantages over current engineered systems, not least of which are time (most biological systems have been around for quite a long time) and resources (most biological systems can produce new resources as they need them e.g. In addition, we need to be very careful as practitioners of bio-inspired techniques that we pay due regard to the actual biological systems and processes. All too often researchers read a little of the biology and charge in applying this to an engineering system without really understanding the biology or the consequences of the simplifications they make. On the other hand, we are not creating biological systems but rather artificial systems.
An exact replication of a complex biological process may neither be needed nor appropriate for the hardware design in question. Improvements in BIAs for EH cannot be justified purely by their “improvements in biological realism”, as may be seen in the literature. Such improvements should be reflected in improvements in the efficiency of the BIA or/and the hardware solutions achievable.It is important to note that biological-like characteristics will be observed in an engineering system that is referred to as bio-inspired but that has in fact little or no real resemblance to the biology that “inspired” it. It is thus important to have a proper framework when using bio-inspired techniques.
A framework for such systems was suggested in and is illustrated in Fig. We are, however, not suggesting that every EH researcher needs to turn to biological experimentation. However, the biological inspiration and validation does need to come from real biological knowledge. Evolvable hardware has, on the whole, been driven by the hardware/technology available at a particular time, and usually this has been electronic hardware.
While the paper is not going to go into great detail on the different hardware platforms, it is at least an important enough driver for the subject to mention a few of the main platforms/devices. These are presented under Analogue and Digital Devices. Analogue devices Field programmable analogue arrays (FPAA)The Lattice Semiconductor ispPAC devices are typical of what is currently available from manufacturers that allow reconfiguration of “standard” analogue blocks (in this case based around OpAmps). The isp family of programmable devices provide three levels of programmability: the functionality of each cell; the performance characteristics for each cell and the interconnect at the device architectural level. Programming, erasing, and reprogramming are achieved quickly and easily through standard serial interfaces.
The device is depicted in Fig. The basic active functional element of the ispPAC devices is the PACell which, depending on the specific device architecture, may be an instrumentation amplifier, a summing amplifier or some other elemental active stage. Analogue function modules, called PACblocks, are constructed from multiple PACells to replace traditional analogue components such as amplifiers and active filters, eliminating the need for most external resistors and capacitors. Requiring no external components, ispPAC devices flexibly implement basic analogue functions such as precision filtering, summing/differencing, gain/attenuation and conversion. An issue for someone wishing to undertake evolution on these devices is the fact that the changes that can be made are at a relatively high functional level i.e.
At the OpAmp level. This, together with the overhead for changing functionality, have limited their use in the EH field. JPL field programmable transistor arrayThe Field Programmable Transistor array, designed by the group at NASA, was the first such analogue device specifically designed with evolvable hardware in mind.
The FPTA has transistor level reconfigurability and supports any arrangement of programming bits without danger of damage to the chip (as is the case with some commercial devices). Three generations of FPTA chips have been built and used in evolutionary experiments. The latest chip, the FPTA-2, consists of an 8 × 8 array of reconfigurable cells (see Fig. ). The chip can receive 96 analogue/digital inputs and provide 64 analogue/digital outputs. Each cell is programmed through a 16-bit data bus/9-bit address bus control logic, which provides an addressing mechanism to download the bit-string of each cell. Each cell has a transistor array (reconfigurable circuitry shown in Fig. ), as well as a set of other programmable resources (including programmable resistors and static capacitors).
The reconfigurable circuitry consists of 14 transistors connected through 44 switches and is able to implement different building blocks for analogue processing, such as two- and three-stage Operational Amplifiers, logarithmic photo detectors and Gaussian computational circuits. It includes three capacitors, Cm1, Cm2 and Cc, of 100fF, 100fF and 5pF, respectively. Heidelberg field programmable transistor array (FPTA)The FPTA consists of 16 × 16 programmable transistor cells. As CMOS transistors come in two types, namely N- and P-MOS, half of the transistor cells are designed as programmable NMOS transistors and half as programmable PMOS transistors. P- and N-MOS transistor cells are arranged in a checkerboard pattern, as depicted in Fig. Each cell contains the programmable transistor itself, three decoders that allow the three transistor terminals to be connected to one of the four cell boundaries, Vdd or Gnd and six routing switches. Width W and Length L of the programmable transistor can be chosen to be 1, 2, 15 μm and 0.6, 1, 2, 4, or 8 μm, respectively.
The three terminals: Drain, Gate and Source, of the programmable transistor can be connected to either of the four cell edges (N, S, E, W), as well as to Vdd or Gnd. The only means of routing signals through the chip is via the six routing switches that connect the four cell borders with each other. Thus, in some cases, it is not possible to use a transistor cell for routing and as a transistor. Digital devices Field programmable gate arrays (FPGA)The FPGA is a standard digital device and is organized as an array of logic blocks, as shown in Fig.
Devices from both Xilinx and Altera have been applied to EH. Programming an FPGA requires programming three tasks: (1) the functions implemented in logic blocks, (2) the signal routing between logic blocks and (3) the characteristics of the input/output blocks i.e. A tri-state output or a latched input. All of these, and hence the complete functionality of the device (including interconnect), are defined by a bit pattern.
Specific bits will specify the function of each logic block, other bits will define what is connected to what. To date FPGAs have been the workhorse of much of EH that has been achieved in the digital domain. The CellMatrix MOD 88As with analogue devices, the other path to implement evolvable hardware is to design and build your own device, tuned to the needs of Evolvable Hardware. The Cell Matrix, illustrated in Fig., is a fine-grained reconfigurable device with an 8 × 8 array of cells, where larger arrays may be achieved by connecting multiple 8 × 8 arrays. Unlike most other reconfigurable devices, there is no built in configuration mechanism.
Aztecs facts. .
Instead each cell is configured by its nearest neighbour, providing a mechanism for not only configuration but also self-reconfiguration and the potential for dynamic configuration. Further, the Cell matrix cannot be accidently damaged by incorrect configurations, as is the case for FPGAs if the standard design rules are not followed. The POEtic deviceThe goal of the “Reconfigurable POEtic Tissue” (“POEtic”) , completed under the aegis of the European Community, was the development of a flexible computational substrate inspired by the evolutionary, developmental and learning phases in biological systems. POEtic applications are designed around molecules, which are the smallest functional blocks (similar to FPGA CLBs). Groups of molecules are put together to form larger functional blocks called cells. Cells can range from basic logic gates to complete logic circuits, such as full-adders.
Finally, a number of cells can be combined to make an organism, which is the fully functional application. Figure shows a schematic view of the organic subsystem. The organic subsystem is constituted from a regular array of basic building blocks (molecules) that allow for the implementation of any logic function. This array constitutes the basic substrate of the system. On top of this molecular layer there is an additional layer that implements dynamic routing mechanisms between the cells that are constructed from combining the functionality of a number of molecules. Therefore, the physical structure of the organic subsystem can be considered as a two-layer organization (at least in the abstract), as depicted in Fig. The RISA deviceThe structure of the RISA cell enables a number of different system configurations to be implemented.
Each cell’s FPGA fabric may be combined into a single area and used for traditional FPGA applications. Similarly, the separate microcontrollers can be used in combination for multi-processor array systems, such as systolic arrays. However, the intended operation is to use the cell parts more locally, allowing the microcontroller to control its adjoining FPGA configuration. This cell structure is inspired by that of biological cells. As illustrated in Fig., the microcontroller provides functionality similar to a cell nucleus.
Each cell contains a microcontroller and a section of FPGA fabric. Input/output (IO) Blocks provide interfaces between FPGA sections at device boundaries. Inter-cell communication is provided by dedicated links between microcontrollers and FPGA fabrics.
There have been some real successes within the community over the past 15 years. This section gives a short review of some of these. Extrinsic analogueSome of the earliest work on using evolutionary algorithms to produce electronic circuits was performed by Koza and his team –.
The majority of this work focused on using Genetic Programming (GP) to evolve passive, and later active, electronic circuits for “common” functions such as filters and amplifiers. All of this work was extrinsic, that is performed in software with the results generally presented as the final fit individual.
Much of the early work considered the design of passive filters with considerable success. Figure illustrates such results. The interesting aspect in this particular paper (that was carried on and developed in subsequent work) was the use of input variables (termed free variables) and conditional statements to allow circuit descriptions to be produced that were solutions to multiple instances of a generic problem, in this case filter design. This is illustrated by specifying, with such input variables, whether a low-pass or high-pass filter is the required final solution of the GP. A more sophisticated example of evolving electronic circuits is shown in Fig. Here the requirement was to create a circuit that mimicked a commercial amplifier circuit (and even improve on it). There are a number of both subtle and complex points that come out of this paper that are of interest and use to others trying to use evolvable hardware.
The paper illustrates how the use of domain knowledge, both general and problem-specific, is important as the complexity of the problem increases. New techniques, or improvements in actual GP techniques were developed to solve this problem. Finally, and potentially most important, the use of multi-objective fitness measures are shown to be critical for the success of evolution. In this case 16 objective measures were incorporated into the evolutionary process, including: gain, supply current, offset voltage, phase margin and bias current. When evolving for real systems in real environments the use of multi-objective fitness criteria is shown to be extremely important.Koza and his group continue to evolve electronic circuits in an extrinsic manner and have many results where the evolutionary process has replicated results of human designs that have been patented in the past. Intrinsic digitalOne of the very first research teams to apply evolvable hardware in an intrinsic manner was Higuchi and his group in Japan , –.
This work included applying evolvable hardware (almost always intrinsically) to myoelectric hands, image compression, analogue IF filters, femto-second lasers, high-speed FPGA I/O and clock-timing adjustment. Here we will give a little more detail on the application of clock-timing adjustment as an illustration of the work conducted by Higuchi and his group.As silicon technology passed the 90 nm process size new problems in the fabrication of VLSI devices started to appear. One of these is the fact that, due to process variations cause by the fabrication process, the clock signals that appear around the chip are not always synchronised with each other. This issue is often called clock skew and can be a major issue in large complex systems.
This is a very difficult issue for chip designers since it is a post fabrication problem where there is a significant stochastic nature to the issues. One solution would of course be to slow the clocks down, but that is generally an unacceptable solution. Another possibility is to treat this as a post-fabrication problem, where actual differences in paths and actual speeds can be measured.Figure illustrates the basic philosophy behind the idea of using evolution to solve this problem. Typically clock signals are transmitted around complex VLSI devices, in a hierarchical form, often known as clock-trees, as illustrated in the left-hand picture in Fig. At the block level (middle picture), sequential circuits should receive clock signals at the same time for the circuit to perform correctly.
The idea behind this work was to introduce programmable delay circuits (right-hand picture) that were able to fine-tune the delay on all the critical path lengths that the clock propagated. The issue is, what delay should be programmed into each individual path on each individual VLSI device? Each device is likely to be different due to the fabrication process and we will not know what this is until after fabrication.
However, the delay can be controlled (programmed) by a short bit pattern stored in a register, on-chip. This bit pattern can form part of a genome that is used within an evolutionary loop that is using a Genetic Algorithm (GA) to optimise the delay in each of the critical paths in the circuit. Figure illustrates in more detail the actual circuit elements required, and the final chip design, to achieve the required functionality for this evolvable chip. The results suggest that not only can the clock skew be optimised, and consequently the frequency that the device can run at be increased (in the paper by 25%) but that also the supply voltage can be reduced while maintaining a functioning chip (in some cases by more than 50%).
Intrinsic analogueSection has already given a brief outline of the work performed by the team at NASA JPL on the design and manufacture of a number of analogue programmable devices aimed at assisting with intrinsic analogue evolution, Field Programmable Transistor Arrays (FPTAs). Here, one of these devices is presented to illustrate, not only the evolution of useful circuits (in real environments), but that through the continued use of evolution throughout the lifetime of the system, fault tolerance is increased. In this case the functionality considered is that of a 4-bit digital-to-analogue converter (4-bit DAC). The basic evolvable block used in these experiments refers back to Fig. In this paper and the results obtained in the work can be seen, summarised, in Fig. Hardware experiments use the FPTA-2 chip, with the structure illustrated in Fig. The process started by evolving first a 2-bit DAC—a relatively simple circuit.
Using this circuit as a building block, a 3-bit DAC was then evolved and again reusing this a 4-bit DAC was evolved. The total number of FPTA cells used was 20. Four cells map a previously evolved 3-bit DAC (evolved from a 2-bit DAC), four cells map a human designed Operational Amplifier (buffering and amplification) and 12 cells have their switches’ states controlled by evolution. When the fault was to be injected into the operating circuit, the system opened all the switches of the 2 cells of the evolved circuit.Figure top-left: The faulty cells are shown in black. In these cells all switches were opened (stuck-at-0 fault).
The 3-bit DAC, cells ‘0’, ‘1’, ‘2’ and ‘3’ map the previously evolved 3-bit DAC, whose output is O3. The Operational Amplifier cell (Label ‘A’) was constrained to OpAmp functionality only.
The evolved cell (in grey) switches’ states were controlled by evolution. O4 is the final output of the 4-bit DAC.Figure, plots: The top-right plot illustrates the initial evolved 4-bit DAC with inputs 1, 2 and 3 (4 is missing due to number of oscilloscope channels) and output O4 which can be seen to be functioning correctly.
The bottom left plot in Fig. Shows the response of the 4-bit DAC when two cells are made faulty. Finally, the plot at the bottom-right of Fig. Illustrates the response of the DAC after further evolution (after fault injection) has taken place.
This response was achieved after only 30 generations of evolution. Again the only cells involved in the evolutionary process are those in grey in Fig. This example shows very well that recovery by evolution, in this case for a 4bit DAC, is possible.
The system made available 12 cells for evolution. Two cells were constrained for the implementation of the OpAmp.
Four cells were constrained to implement the simpler 3bit DAC. Two faulty cells were implemented by placing all their switches to the open position.
Extrinsic and intrinsic analogueAs a final example in this section, the domain of evolved antenna design is presented. In the work presenter in , a GA was used in conjunction with the Numerical Electromagnetic Code, Version 4 (NEC, standard code within this area) as the simulator to create and optimize wire antenna designs. These designs not only produced impressive characteristics, in many cases similar.
(redirected from Evolvable hardware)Also found in: Wikipedia.
| Acronym | Definition |
|---|---|
| EH | English Heritage |
| EH | Economic History (economics) |
| EH | East Hampton |
| EH | Redox Potential |
| EH | Environmental Hazards (various organizations) |
| EH | Event Horizon |
| EH | Edinburgh, Scotland (postal code) |
| EH | Exception Handling (programming technique) |
| EH | English Horn |
| EH | Environmental Safety and Health |
| EH | Evolvable Hardware |
| EH | Euskal Herritarrok (leftist Basque nationalist group) |
| EH | Electric Heater |
| EH | Ernie Hudson (actor) |
| EH | Eastern Hemisphere (airline code) |
| EH | Espresso House (coffee chain; Sweden) |
| EH | Extra Hazardous |
| EH | East Hanover (New Jersey) |
| EH | Extra Hitter (added hitter used in Babe Ruth baseball) |
| EH | England Hockey |
| EH | Emotionally Handicapped |
| EH | Ekoostik Hookah (musical group) |
| EH | Electric Hoist |
| EH | Electronic Harassment |
| EH | Endress-Hauser |
| EH | Emperor's Hammer (Star Wars gaming fan group) |
| EH | Ehrenhalber (German: Honoris Causa) |
| EH | Escort Helicopter |
| EH | Engineering House |
| EH | Emerald Heights (retirement home) |
| EH | English Hardness (water) |
| EH | Ebon Hawk (Star Wars ship) |
| EH | Eusoff Hall (National University of Singapore) |
| EH | Sahara Español (Western Sahara, ISO code) |
| EH | Empty Height |
| EH | Eastern Hancock (high school) |
| EH | Enfield Homes (Enfield, UK) |
| EH | Electronic Warfare Helicopter (US Army) |
| EH | Equivalent Hertz |
| EH | Exercise Head |
| EH | Evaluation Headquarters |
| EH | Engrossed in the House of Representatives (bill status) |
| EH | Encyclopedia Holistica |
| EH | Symbol for standard oxidation-reduction potential |
| EH | Extremely High Risk Rating |
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